1. Field of the Invention
The present invention relates generally to methods for fabricating microelectronic fabrications. More particularly, the present invention relates to methods for forming crack resistant planarizing layers when fabricating microelectronic fabrications.
2. Description of the Related Art
Within the general art of microelectronic fabrication, there exist purely electronic microelectronic fabrications whose operation is based solely upon electrical signal storage and processing characteristics of purely electronic microelectronic devices and microelectronic circuits formed upon a microelectronic substrate. Examples of such purely electronic microelectronic fabrications typically include, but are not limited to, semiconductor integrated circuit microelectronic fabrications and ceramic substrate microelectronic fabrications. Similarly, there also exist within the general art of microelectronic fabrication microelectronic fabrications whose operation is based upon a codependent transduction, storage and/or processing of optical and electrical signals while employing optoelectronic microelectronic devices formed upon a microelectronic substrate. Examples of such optoelectronic microelectronic fabrications typically include, but are not limited to: (1) solar cell optoelectronic microelectronic fabrications; and (2) image array optoelectronic microelectronic fabrications such as but not limited to: (a) sensor image array optoelectronic microelectronic fabrications; and (b) display image array optoelectronic microelectronic fabrications.
Common to all microelectronic fabrications, whether purely electronic microelectronic fabrications or optoelectronic microelectronic fabrications, is the use of planarizing layers for purposes of providing planar surfaces upon which may be formed additional microelectronic layers and additional microelectronic structures within a microelectronic fabrication.
While planarizing layers are thus desirable in the art of microelectronic fabrication and often essential in the art of microelectronic fabrication, planarizing layers are nonetheless not entirely without problems in the art of microelectronic fabrication.
In that regard, it is often difficult in the art of microelectronic fabrication to form within microelectronic fabrications planarizing layers with enhanced planarity and diminished thicknesses.
It is thus desirable in the art of microelectronic fabrication to form within microelectronic fabrications planarizing layers with enhanced planarity and diminished thicknesses.
It is towards the foregoing object that the present invention is directed.
Various applications of planarizing layers within microelectronic fabrications have been disclosed within in the art of microelectronic fabrication. Included in particular among the applications, but not limiting among the applications, are applications related to color filter image array optoelectronic microelectronic fabrications. Specific examples of such applications are disclosed within: (1) McColgin et al., in U.S. Pat. No. 4,553,153; (2) Park et al., in U.S. Pat. No. 5,053,298; and (3) Daly et al., in U.S. Pat. No. 5,654,202, the disclosures of which are incorporated herein fully by reference.
Desirable in the art of microelectronic fabrication are additional methods for forming within microelectronic fabrications planarizing layers with enhanced planarity and diminished thicknesses.
It is towards the foregoing object that the present invention is directed.
A first object of the invention is to provide a method for forming a planarizing layer within a microelectronic fabrication.
A second object of the present invention is to provide a method in accord with the first object of the present invention, wherein the planarizing layer is formed with enhanced planarity and diminished thickness.
In accord with the objects of the present invention, there is provided by the present invention a method for fabricating a microelectronic fabrication.
To practice the method of the present invention, there is first provided a substrate having formed thereover a topographic feature. There is then formed upon the substrate including the topographic feature a planarizing layer formed from a negative photoresist planarizing material. There is then partially photoexposed the planarizing layer to form a partially photoexposed planarizing layer. There is then formed upon the partially photoexposed planarizing layer a sacrificial layer. Finally, there is then sequentially: (1) stripped the sacrificial layer from the partially photoexposed planarizing layer; and (2) developed the partially photoexposed planarizing layer to form a developed planarizing layer planarizing the topographic feature.
The present invention provides a method for forming a planarizing layer within a microelectronic fabrication, wherein the planarizing layer is formed with enhanced planarity and diminished thickness.
The present invention realizes the foregoing object by employing within a microelectronic fabrication, formed upon a partially photoexposed planarizing layer formed of a partially photoexposed negative photoresist material, a sacrificial layer such that when sequentially: (1) stripping from the partially photoexposed planarizing layer the sacrificial layer; and (2) developing the partially photoexposed planarizing layer to form a developed planarizing layer, the developed planarizing layer is formed with enhanced planarity and diminished thickness.